Using Gate Sizing to Reduce Glitch Power

| With the growing scale of integration and the increased use of battery operated devices the power dissipation of CMOS circuits becomes an important factor in the design process. Power dissipation in CMOS-gates depends on the capacity switched and the transition density. Gate sizing is used to scale gates and their internal capacities. Smaller gates mean smaller capacities and therefore less power. Gate sizing however also changes the timing of the circuit and therefore the transition density. To complicate matters CMOS-gates also exhibit a ltering eeect for signals with a period shorter than the propagation delay of the gate. We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the ltering effect of CMOS-gates avoids superruous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a delay balanced circuit are the same as the transition densities calculated with a zero delay model. Guaranteeing a transition density as calculated with a zero delay model makes logic decomposition and technology mapping for low power much easier and makes the much used zero delay model assumption in logic decomposition and technology mapping for low power more valid.